2024

• Z. Gao, F.-K. Sun, R. Rohrer, and D. Boning, “KirchhoffNet: A Scalable Ultra Fast Analog Neural Network,” to be presented, International Conference on Computer-Aided Design (ICCAD), New York, NY, Nov. 2024. **
• E. Bender, J. Bernstein, and D. Boning, “Statistical Degradation in BGAs for Early Fault Detection,” to be presented, International Symposium for Testing and Failure Analysis (ISTFA), San Diego, CA, Oct.-Nov. 2024.
• U. Chakraborty, Z. Gao, and D. S. Boning, “Robust Bayesian Optimization of a Photonic Y-splitter Using a Tunable Acquisition Function,” to be presented Frontiers in Optics + Laser Science (FiO LS), Denver, CO, Sept. 2024. **
• Z. Gao, D. Zhang, L. Daniel, and D. Boning, “NOFIS: Normalizing Flow for Rare Circuit Failure Analysis,” Design Automation Conference (DAC), San Francisco, CA, June 2024. **
• Owens, R., F.-K. Sun, C. Venditti, D. Blake, J. Dillon, and D. Boning, “Dynamic Time Warping Constraints for Semiconductor Processing,” Advanced Semiconductor Manufacturing Conference (ASMC), Albany, NY, May 2024. **
• Ma, P., H. Yang, Z. Gao, D. Boning, and J. Gu, “PIC2O-Sim: A Physics-Inspired causality-Aware Dynamic Convolutional Neural Operator for Ultra-Fast Photonic Device FDTD Simulation,” submitted to Advances in Neural Information Processing Systems (NeurIPS), May 2024. **
• Zheng, S., Z. Gao, F.-K. Sun, D. S. Boning, and M. Wong, “Improving Neural ODE Training with Temporal Adaptive Batch Normalization,” submitted to Advances in Neural Information Processing Systems (NeurIPS), May 2024. **

2023

• C.-Y. Lai, F.-K. Sun, Z. Gao, D. S. Boning, and J. H. Lang, “Nominality Score Conditioned Time Series Anomaly Detection by Point/Sequential Reconstruction,” Advances in Neural Information Processing Systems (NeurIPS), New Orleans, LA, Dec. 2023. **
• J. Gu, M. Dighamber, Z. Gao, and D. S. Boning, “Benchmarking the Robustness of Neural Network-based Partial Differential Equation Solvers,” Fast Machine Learning for Science Workshop, co-located with International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, Nov. 2023. **
• Z. Gao, L. Wilding, A. Burazer, L. Daniel, and D. S. Boning, “Achieving Small False Positive Rate for Automated Visual Inspection via a Dual-Threshold Convolutional Neural Network,” 2023 PDA Visual Inspection Forum, Baltimore, MD, April 2023. **
• E. Bender, J. Bernstein, and D. S. Boning, “The Effects of Process Variation EffectsandBTI inPackaged FinFET Devices,” 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, Mar. 2023.
• Z. Zhang, M. Notaros, Z. Gao, U. Chakraborty, J. Notaros, and D. S. Boning, “Impact of Spatial Variations on Splitter-Tree-Based Integrated Optical Phased Arrays,” Optical Fiber Communications Conference (OFC) 2023, paper W2A.35,San Diego, CA, Mar. 2023.**

2022

• J. Gu, Z. Gao, C. Feng, H. Zhu, R. Chen, D. S. Boning, and D. Z. Pan, “NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation,” to be presented, Advances in Neural Information Processing Systems (NeurIPS), New Orleans, LA, Nov.-Dec. 2022. **
• Z. Gao, X. Chen, Z. Zhang, U. Chakraborty, W. Bogaerts, and D. Boning, “Automatic Realization of Light Processing Functions for Programmable Photonics,” to be presented, 2022 IEEE Photonics Conference (IPC), Vancouver, Canada, Nov. 2022. **
• Z. Gao, F.-K. Sun, M. Yang, S. Ren, Z. Xiong, M. Engeler, A. Burazer, L. Wildling, L. Daniel, and D. S. Boning, “Learning from Multiple Annotator Noisy Labels via Sample-wise Label Fusion,” to be presented, 17^th European Conference on Computer Vision (ECCV), Tel Aviv, Israel, Oct. 2022. Also arXiv 2207.11327. **
• Z. Liang, H. Wang, J. Cheng, Y. Ding, H. Ren, Z. Gao, Z. Hu, D. Boning, X. Qian, S. Han, W. Jiang, and Y. Shi, “Variational Quantum Pulse Learning,” to be presented, IEEE International Conference on Quantum Computing and Engineering (QCE), Broomfield, CO, Sept. 2022. **
• F.-K. Sun, and D. S. Boning, “FreDo: Frequency Domain-based Long-Term Time Series Forecasting,” submitted to Advances in Neural Information Processing Systems (NeurIPS), May 2022. **
• Z. Zhang, S. I. El-Henawy, C. Rios, and D. S. Boning, “Inference of Process Variations in Silicon Photonics from Characterization Measurements,” Conference on Lasers and Electro-Optics (CLEO), San Jose, CA, May 2022. **
• Z. Gao, Z. Zhang, and D. Boning, “Automatic Design of a Broadband Directional Coupler via Bayesian Optimization,” Conference on Lasers and Electro-Optics (CLEO), San Jose, CA, May 2022. **

2021

• F.-K. Sun, C. I. Lang, and D. S. Boning, “Adjusting for Autocorrelated Errors in Neural Networks for Time Series Regression and Forecasting,” Advances in Neural Information Processing Systems (NeurIPS), Dec. 2021. **
• C. I. Lang, D. Boning, R. Sprenkle, E. Wilson, and A. Samolov, “Machine Learning-Based Optimization of Dose Uniformity for Ion Implantation Systems,” AEC/APC Symposium Asia 2021, Nov. 2021. **
• D. Boning, S. E. El-Henawy, and Z. Zhang, “Process Variation-Aware Photonic Design,” OFC 2021, June 2021. **
• H. Zhang, H. Chen, D. S. Boning, and C.-J. Hsieh, “Robust Reinforcement Learning on State Observations with Learned Optimal Adversary,” International Conference on Learning Representations (ICLR), May 2021. **
• F.-K. Sun, C. I. Lang, and D. S. Boning, “Adjusting for Autocorrelated Errors in Neural Networks for Time Series Regression and Forecasting,” submitted to International Conference on Machine Learning (ICML), Jan. 2021. **

2020

• H. Zhang, H. Chen, C. Xiao, B. Li, M. Liu, D. Boning, and C.-J. Hsieh, “Robust Deep Reinforcement Learning against Adversarial Perturbations on Observations,” Advances in Neural Information Processing Systems (NeurIPS), vol. 33, Dec. 2020. (Spotlight presentation.) **
• H. Chen, S. Si, Y. Li, C. Chelba, S. Kumar, D. Boning, and C.-J. Hsieh, “Multi-Stage Influence Function,” Advances in Neural Information Processing Systems (NeurIPS), vol. 33, Dec. 2020. 
• Zhang, Z., S. I. El-Henawy, R. Miller, and D. S. Boning, “Decomposed Representation of S-Parameters for Silicon Photonic Variation Analysis,” SPIE Optics + Photonics, Optical Modeling and Performance Predictions XI, Proc. Vol. 11484, p. 1148408, Online, Aug. 2020. **
• M. B. Alawieh, D. Boning and D. Z. Pan, “Wafer Map Defect Patterns Classification using Deep Selective Learning,” accepted to ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.
• Y. Wang, H. Zhang, H. Chen, D. Boning, and C.-J. Hsieh, “On Lp-norm Robustness of Ensemble Decision Stumps and Trees,” International Conference on Machine Learning (ICML), pp. 10104-10114, July 2020. **
• H. Chen, Y. Wang, H. Zang, C.-J. Hsieh, S. Si, Y. Li, and D. Boning, “Robustness Verifications for Ensemble Stumps and Trees,” 3^rd Workshop on Formal Methods for ML-Enabled Autonomous Systems (FoMLAS 2020), July 20, 2020. **
• M. B. Alawieh, M. D. Boning and D. Z. Pan, “Wafer Map Defect Patterns Classification using Deep Selective Learning,” 57^th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.
• H. Zhang, H. Chen, C. Xiao, S. Gowal, R. Stanforth, B. Li, D. Boning, and C.-J. Hsieh, “Towards Stable and Efficient Training of Verifiably Robust Neural Networks” International Conference on Learning Representations (ICLR), May 2020. **

2019

• H. Chen, H. Zhang, S. Si, Y. Li, D. Boning, and C.-J. Hsieh, “Robustness Verification of Tree-based Models,” Thirty-third Conference on Neural Information Processing Systems (NeurIPS), Vancouver, Canada, Dec. 2019. **
• S. El-Henawy, C. Lang, and D. Boning, “Yield Prediction for Coupled-Resonator Optical Waveguides Using Variation-Aware Compact Models,” in Frontiers in Optics + Laser Science APS/DLS, OSA Technical Digest (Optical Society of America, 2019), Washington, DC, Sept. 2019. *
• Z. Zhang, M. B. McIlrath, and D. S. Boning, “Adjoint-based Particle Defect Yield Modeling for Silicon Photonics,” Proc. SPIE 11103, Optical Modeling and System Alignment, 111030Q, Sept. 2019.
• S. I. El-Henawy, Z. Zhang, R. Miller, and D. S. Boning, “Photonic Device Sensitivity Analysis Methods: Towards Process Variation-aware Silicon Photonics Design,” SPIE Optics+Photonics, Optical Modeling and System Alignment 11103, San Diego, CA, Aug. 2019.**
• H. Chen, H. Zhang, D. S. Boning, and C.-J. Hsieh, “Robust Decision Trees Against Adversarial Examples,” International Conference on Machine Learning (ICML), June 2019.**
• H. Chen, H. Zhang, S. Si, Y. Li, D. Boning, and C.-J. Hsieh, “Robustness Verification of Tree-based Models,” Workshop on the Security and Privacy of Machine Learning (SPML), Long Beach, CA, June 2019.
• H. Chen, H. Zhang, D. Boning, and C.-J. Hsieh, “Adversarial Defense for Tree-Based Models,” SafeML Workshop at International Conference on Learning Representations (ICLR), New Orleans, LA, May 2019.
• H. Zhang, S. I. El-Henawy, A. Sadun, R. Miller, L. Daniel, J. K. White, and D. S. Boning, “Adjoint-Based Sensitivity Analysis for Silicon Photonic Variations,” IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), Cambridge, MA, May 2019.
• H. Zhang, H. Chen, Z. Song, D. S. Boning, I. S. Dhillon, and C.-J.Hsieh, “The Limitations of Adversarial Training and the Blind-Spot Attack,” International Conference on Learning Representations (ICLR), New Orleans, LA, May 2019.

2018

• S. Elhenawy, R. Miller, and D. S. Boning, “Effects of a Random Process Variation on the Transfer Characteristics of a Fundamental Photonic Integrated Circuit Component,” Optical Modeling and Performance Predictions X, SPIE Optical Engineering + Applications, vol. 107430, pp. 107430O-1–107430O-10, San Diego, CA, Aug. 2018.
• W. Weng. T. W., H. Zhang, H. Chen, Z. Song, C.-J. Hsieh, L. Daniel, D. Boning, and I. S. Dhillon, “Towards Fast Computation of Certified Robustness for ReLU Networks,” International Conference on Machine Learning (ICML), Stockholm, Sweden, July 2018.
• C. Lang and D. Boning, “Modelling Pattern Dependent Variations in Semi-Additive Copper Electrochemical Plating,” IEEE Advanced Semiconductor Manufacturing Conference (ASMC), Sarasota Springs, NY, May 2018.

2017

• H. Chen and D. S. Boning, “Online and incremental machine learning approaches for IC yield improvement,” in Proceedings of the 36th International Conference on Computer-Aided Design (ICCAD ’17). IEEE Press, Piscataway, NJ, USA, 786-793. Nov. 2017.
• D. S. Boning, “It’s Time to Learn About Silicon Photonics,” Keynote Address, CDNLive Conference, Aug. 2017.
• C. Lang and D. S. Boning, “Spin Coating Modeling and Planarization Using Fill Patterns for Advanced Packaging Technologies,” IEEE Advanced Semiconductor Manufacturing Conference (ASMC), May 2017.

2016

• H. Chen, D. Boning, and Z. Zhang, “Efficient Spatial Variation Characterization via Matrix Completion,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), Austin, TX, Nov. 2016. **

2015

• D. Boning, W. Fan, Y. Zhuang, Y. Sampurno, and A. Philipossian, “Planarization with Suspended Polyurethane Beads and a Stiff Counterface: Pad-in-a-Bottle Experiments and Simulation,” International Conference on Planarization Technology (ICPT), Phoenix, AZ, Oct. 2015. **
• J. H. Lee, J. Jimenez, I. R. Butterworth, C. Castro-Gonzalez, S. K. Shukla, B. Marti-Fuster, L. Elvira, D. S. Boning, and B. W. Anthony, “Measurement of Very Low Concentration of Microparticles in Fluid by Single Particle Detection using Acoustic Radiation Force Induced Particle Motion,” 2015 IEEE International Ultrasonics Symposium (IUS), Taipei, Taiwan, Oct. 2015. **
• J. H. Lee, J. Jimenez, X. Zhang, D. S. Boning, and B. W. Anthony, “Ultrasound Image-based Absolute Concentration Measurement Technique for Materials with Low Scatterer Concentration,” 2015 IEEE International Ultrasonics Symposium (IUS), Taipei, Taiwan, Oct. 2015. **
• L. Yu, I. Elfadel, and D. Boning, “Efficient IC Statistical Modeling and Extraction using a Bayesian Inference Framework,” ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2015), Monterey, CA, March 2015. **
• L. Yu, I. Elfadel, and D. Boning, “Statistical Library Characterization Using Belief Propagation across Multiple Technology Nodes,” Design, Automation & Test in Europe (DATE), pp. 1383-1388, Grenoble, France, March 2015. **
• H. Y. Boo, D. S. Boning, and H.-S. Lee,, “12b 250MS/S pipelined ADC with virtual ground reference buffers,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 282-283, San Francisco, CA, Feb. 2015. **

2014

• L. Yu, I. Elfadel, D. Antoniadis, and D. Boning, “Optimal selection of measurements for statistical transistor compact model extraction,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), Santa Clara, CA, Nov. 2014. **
• Lee, J. H., C. M. Schoelhammer, G. Traverso, D. Blankschtein, R. Langer, B. Anthony, and D. S. Boning, “Towards Wireless Capsule Endoscopic Ultrasound (WCEU),” 2014 IEEE International Ultrasonics Symposium (IUS), Chicago, IL, Sept. 2014. **
• L. Yu, S. Saxena, C. Hess, I. Elfadel, D. Antoniadis, and D. Boning, “Remembrance of Transistors Past: Compact Model Parameter Extraction Using Incomplete New Measurements and a Bayesian Framework,” Design Automation Conference (DAC), San Francisco, CA, June 2014. **
• Flounders, A. W. and D. Boning, “The University Microfabrication Laboratory Network,” IEEE University, Government, Industry Micro/Nano Technology Symposium (UGIM 2014), Cambridge, MA, June 2014.
• L. Yu, S. Saxena, C. Hess, I. Elfadel, D. Antoniadis, and D. Boning, “Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation,” Design, Automation & Test in Europe (DATE), article no. 226, Dresden, Germany, March 2014. **

2013

• L. Yu, O. Mysore, L. Wei, L. Daniel, D. A. Antoniadis, I. Elfadel, and D. Boning, “An Ultra-Compact Virtual Source FET Model for Deeply-Scaled Devices: Parameter Extraction and Validation for Standard Cell Libraries and Digital Circuits,” 18th Asia and South Pacific Design Automation Conferences (ASP-DAC), pp. 521-526, Yokohama, Japan, Jan. 2013. **
• L. Yu, O. Mysore, L. Wei, L. Daniel, D. A. Antoniadis, I. Elfadel, and D. Boning, “Statistical Modeling with the Virtual Source MOSFET Model,” Design, Automation & Test in Europe (DATE), pp. 1454-1457, Grenoble, France, March 2013. **
• Fan, W., J. Johnson, and D. S. Boning, “Modeling of ‘Pad-in-a-Bottle’: A Novel Planarization Process Using Suspended Polymer Beads,” Symposium BB: Evolutions in Planarization – Equipment, Materials, Techniques and Applications, Materials Research Society Spring Meeting, MRS Symposium Proceedings vol. 1560, 10 pages, San Francisco, CA, March 2013. **
• A. Chang, H.-S. Lee, and D. Boning, “A 12b 50MS/s 2.1mW SAR ADC with Redundancy and Digital Background Calibration,” 2013 European Solid-State Circuits Conference (ESSCIRC), pp. 109-112, Sept. 2013. **
• T. Tekeste, A. Shabra, D. Boning, and I. Elfadel, “Variability Analysis of a 28nm Near Threshold Synchronous Voltage Converter,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), Santa Clara, CA, Nov. 2013.
• T. Tekeste, A. Shabra, D. Boning, and I. Elfadel, “Variability Analysis of a 28nm Near Threshold Synchronous Voltage Converter,” 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), pp. 723-726, Abu Dhabi, UAE, Dec. 2013.
• Chang, A., H.-S. Lee, and D. Boning, “A 12b 50MS/s 2.1mW SAR ADC with Redundancy and Digital Background Calibration,” Student Research Preview, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013. ** Session Award: Honorable Mention

2012

• A. H. Chang, K. Zuo, J. Wang, D. Yu, and D. Boning, “Test Structure, Circuits and Extraction Methods to Determine the Radius of Influence of STI and Polysilicon Pattern Density,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 185-192, March 2012. **
• L. Yu, W.-Y. Chang, K. Zuo, J. Wang, D. Yu, and D. Boning, “Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 216-222, March 2012. **
• W. Zhang, K. Balakrishnan, X. Li, D. Boning, E. Acar, F. Liu, and R. A. Rutenbar, “Spatial Variation Decomposition via Sparse Regression,” International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2012. **
• J. M. Johnson, D. S. Boning, G.-S. Kim, P. Safier, K. Knutson, “Slurry Abrasive Particle Agglomeration Experimentation and Modeling for Chemical Mechanical Planarization (CMP),” International Conference on Planarization Technology (ICPT), Grenoble, France, Oct. 2012. **
• L. Yu, O. Mysore, L. Wei, L. Daniel, D. A. Antoniadis, I. Elfadel, and D. Boning, “Virtual Source MOSFET Model: Parameter Extraction, Statistical Modeling and Application,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), Santa Clara, CA, Nov. 2012. **

2011

• K. Balakrishnan, K. Jenkins, and D. Boning, “A Simple Array-Based Test Structure for the AC Variability Characterization of MOSFETs,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 539-544, March 2011. **
• A. H. Chang, D. Boning, and H.-S. Lee, “Redundancy in SAR ADCs,” Great Lakes Symposium on Very Large Scale Integration (GLSVLSI), pp. 283-288, Lausanne, Switzerland, May 2011. **
• K. Balakrishnan, K. A. Jenkins, and D. Boning, “A Ring Oscillator-Based Test Structure for AC Variability Characterization of Individual MOSFETs,” 2nd European Workshop on CMOS Variability (VARI), 4 pages, Grenoble, France, May 2011. ** Best Paper Award, Industry Relevance
• W. Y. Zhang, K. Balakrishnan, X. Li, D. Boning, and R. Rutenbar, “Toward Efficient Spatial Variation Decomposition via Sparse Regression,” IEEE International Conference on Computer-Aided Design (ICCAD), pp. 162-169, Nov. 2011. **
• W. Fan, D. Boning, Y. Zhuang, Y. Sampurno, A. Philipossian, M. Moinpour and D. Hooper, “Characterization of CMP Pad Surface Properties and Aging Effects,” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011. **
• J. Johnson, D. Boning, G.-S. Kim, R. Mudhivarthi, P. Safier, and K. Pate, “Slurry Particle Agglomeration Model for Chemical Mechanical Planarization (CMP),” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011. **

2010

• J. O. Diaz, H. K. Taylor, R. J. Shul, R. L. Jarecki, T. M. Bauer, D. S. Boning, and D. L. Hetherington, “A Computationally Simple, Wafer-to-Feature-Level Model of Etch Rate Variation in Deep Reactive Ion Etching,” AVS 57th International Symposium and Exhibition, Albuquerque, NM, Oct. 2010. **
• D. Boning, A. H. Chang, K. Zuo, J. Wang, and D. Yu, “Test Structures, Circuits, and Extraction Methods for Determining Pattern Density Effects,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), San Jose, CA, Nov. 11, 2010. **
• H. Taylor, K. Simstrup, and D. Boning, “Modeling the Enhancement of Nanoimprint Stamp Bending Compliance by Backside Grooves: Mitigating the Impact of Wafer Nanotopography on Residual Layer Thickness,” 9^th International Conference on Nanoimprint and Nanoprint Technology (NNT), Copenhagen, Denmark, Oct. 2010. **
• D. Boning, A. Kahng, H. Taylor, and Y.-K. Wu, “Chip-Scale Simulation of Residual Layer Thickness Uniformity in Thermal Nanoimprint Lithography: Evaluating Stamp Cavity-Height and ‘Dummy-Fill’ Selection Strategies,” 9^th International Conference on Nanoimprint and Nanoprint Technology (NNT), Copenhagen, Denmark, Oct. 2010. **
• H. Taylor, K. Smistrup, and D. Boning, “Modeling and simulation of stamp deflections in nanoimprint lithography: exploiting backside grooves to enhance residual layer thickness uniformity,” 36th International Conference on Micro & Nano Engineering (MNE2010), Genoa, Sept. 2010. **
• W. Fan, J. Johnson, and D. S. Boning, “Non-Ohmic Wafer-Level Modeling of Electrochemical-Mechanical Planarization (ECMP),” International Conference on Planarization Technology (ICPT), Phoenix, AZ, Oct. 2010. **
• Fan, W., J. Johnson, and D. Boning, “Wafer-level Modeling of Electrochemical-Mechanical Planarization (ECMP),” International Conference on Planarization Technology (ICPT), Phoenix, AZ, Oct. 2010. **
• D. Boning and W. Fan, “Characterization and Modeling of Pad Asperity Response in CMP,” paper E5.4, Chemical-Mechanical Planarization Symposium, MRS Spring Meeting, vol. 1249, pp. 147-154, San Francisco, April 2010. **
• D. Boning and J. M. Johnson, “Slurry Particle Agglomeration Model for Chemical Mechanical Planarization (CMP),” paper E4.3, Chemical-Mechanical Planarization Symposium, MRS Spring Meeting, vol. 1249, pp. 103-112, San Francisco, April 2010. **
• D. Boning, “CMP Mechanisms and Models: Progress and Challenges,” Keynote, Symposium V: CMP and Post-CMP Cleaning, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, March 18-19, 2010. **
• H. Taylor and D. Boning, “Towards nanoimprint lithography-aware layout design checking,” SPIE Advanced Lithography, Design for Manufacturability through Design-Process Integration IV, Proc. of SPIE Vol. 7641, paper 7641-29 (12 pages), San Jose, CA, Feb. 2010. **
• Anthony, B. W., D. S. Boning, S. F. Yoon, K. Youcef-Toumi, Z. P. Fang, D. Ljubicic, S. Li, I. Reading, V. Shilpiekandula, H. K. Taylor, Z. Xu, and J. Zhao, “Metrology and Process Control for Manufacturing of Microfluidic Devices,” Symposium on Manufacturing of Microfluidic Devices, NTU, Singapore, January 21, 2010. **
• Fan, W., D. Boning, Y. Zhuang, Y. Sampurno, A. Philipossian, D. Hooper, and M. Moinpour, “Characterization of CMP Pad Surface Properties,” Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 2010. **

2009

• H. Taylor and D. Boning, “Fast simulation of pattern dependencies in thermal nanoimprint lithography,” International Conference on Nanoimprint and Nanoprint Technology (NNT), paper C14 (2 pages), San Jose, CA, Nov. 2009. **
• K. Balakrishnan and D. Boning, “Measurement and Analysis of Contact Plug Resistance Variability,” Custom Integrated Circuits Conference (CICC), pp. 415-422, San Jose, CA, Oct. 2009. **
• Boning, D., J. Johnson, H. McCulloh, and N. Patel, “The Evolution of Pattern-Density in CMP Modeling,” Symposium E: Science and Technology of Chemical Mechanical Planarization (CMP), Materials Research Society Spring Meeting, San Francisco, CA, April 2009. **

2008

• H. Taylor, D. S. Boning, C. I. Iliescu, B. Chen, Y.-C. Lam, and X. Chen, “Modeling Pattern Dependencies in the Micro-scale Embossing of Polymeric Layers,” Micro- and Nanotechnology: Materials, Processes, Packaging, and Systems IV, Proc. of SPIE, Vol. 7269, Melbourne, Australia, Dec. 2008. **
• N. Drego, A. Chandrakasan, and D. Boning, “An All-Digital, Highly Scalable Architecture for Measurement of Spatial Variation in Digital Circuits,” IEEE Asian Solid-State Circuit Conference (ASSCC), Fukuoka, Japan, Nov. 2008. **
• H. Taylor and D. Boning, “An Integrated Crack-Opening Method for Determining the Work of Fracture of Bonded Polymer Interfaces,” 12^th International Conference on Miniaturized Systems for Chemistry and Life Sciences (microTAS 2008), San Diego, CA, Oct. 2008. **
• H. K. Taylor, Z. Xu, L. Shiguang, K. Youcef-Toumi, S. F. Yoon, and D. S. Boning, “Moire fringe method for the measurement of distortions of hot-embossed polymeric substrates,” to be presented, 9^th International Symposium on Laser Metrology, Singapore, June-July 2008. **
• H. K. Taylor and D. S. Boning, “Diffraction-based Approaches to the In-situ Measurement of Dimensional Variations in Components Produced by Thermoplastic Micro- and Nano-embossing,” 5^th International Symposium on Nanomanufacturing, Singapore, Jan. 2008. **
• Z. G. Xu, S. G. Li, S. F. Yoon, Z. P. Fang, K. Youcef-Toumi, D. J. Burns, V. Shilpiekandula, H. K. Taylor and D. S. Boning, “Complete Surface Distinguishing and Overlapping Technology for Three-dimensional Image Processing of Micro Devices,” 5^th International Symposium on Nanomanufacturing, Singapore, Jan. 2008. **
• A. Philipossian, Y. Sampurno, L. Borucki, Y. Zhuang, S. Misra, K. Holland, and D. Boning, “Characterization of Thermoset and Thermoplastic Polyurethane Pads, and Molded and Non-optimized Machined Grooving Methods for Oxide CMP Applications,” Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 2008.
• Boning, D. , K. Balakrishnan, A. Chang, N. Drego, W. Fan, J. Johnson, and H. Taylor, “Measuring and Modeling IC Variability at the Process, Device, and Circuit Levels,” ICCAD Workshop on Test Structure Design for Variability Characterization (TSD), San Jose, CA, Nov. 2008.

2007

• Z. Li, D. Truque, D. Boning, R. Caramto, and C. Borst, “Modeling Wafer Level Uniformity in Electrochemical-Mechanical Polishing (ECMP),” Advanced Metallization Conference (AMC), pp. 131-135, Albany, NY, Oct. 2007. **
• H. Taylor, B. Chen, C. Iliescu, and D. Boning, “Computationally efficient modeling of pattern dependencies in the micro-embossing of thermoplastic polymers,” 33^rd International Conference on Micro- and Nano-Engineering, Copenhagen, Denmark, September 2007. **
• D. Lim, J. Kim, J.-O. Plouchart, D. Kim, C. Cho, and D. S. Boning, “Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS,” 2007 IEEE Radio-Frequency Integrated Circuits (RFIC) Symposium, June 2007. **
• S. P. Vudathu, D. Boning, and R. Laur, “A Critical Enhancement in the Yield Analysis of Microsystems,” International Reliability Physics Symposium (IRPS), April 2007. **
• D. Truque, X. Xie, and D. Boning, “Wafer Level Modeling of Electrochemical-Mechanical Polishing (ECMP),” CMP Symposium, MRS Spring Meeting, April 2007. **
• X. Xie and D. Boning, “Physical-based Die-level CMP Model,” CMP Symposium, MRS Spring Meeting, April 2007. **
• N. Drego, A. Chandrakasan, and D. Boning, “A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2007. **
• K. Gettings and D. Boning, “Test Circuit for Study of CMOS Process Variation by Measurement of Analog Characteristics,” International Conference on Microelectronic Test Structures (ICMTS), pp. 37-41, Tokyo, Japan, March, 2007. **
• D. Boning, K. Balakrishnan, H. Cai, N. Drego, A. Farahanchi, K. Gettings, D. Lim, A. Somani, H. Taylor, D. Truque, and X. Xie, “Variation,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2007. **
• H. Cai and D. Boning, “In-Pattern Dummy Design and Copper ECD/CMP Process Co-optimization,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Fremont, CA, Feb. 2007. **
• D. Lim, J. Kim, J.-O. Plouchart, C. Cho, D. Kim, R. Trzcinski, and D. Boning, “Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS Technology,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2007. **
• D. Boning, “Chip-Scale Modeling of CMP and Plating Processes,” Fourth International Copper Interconnect Technology Symposium, Fudan University, Shanghai, China, May 2007. Also at Tsinghua University, Beijing, China, May 2007. **
• D. Boning, “Modeling of Chip-Scale Pattern Dependencies in Interconnect Fabrication Processes,” Advanced Metallization Conference, Albany, NY, Oct. 2007. **

2006

• X. Xie, D. Boning, F. Meyer, and R. Rzehak, “Analysis of Nanotopography and Layout Variations in Patterned STI CMP,” International Conference on Planarization Technology (ICPT), Foster City, CA, Oct. 2006. **
• Somani, D. Boning, P. Gschwend and R. Reif, “Environmental Impact Evaluation Methodology for Emerging Silicon-Based Technologies,” International Symposium on Electronics and the Environment, San Francisco, May 2006. **
• Abrokwah, K. O., P. R. Chidambaram, and D. S. Boning, “Pattern Based Prediction for Plasma Etch,” Advanced Semiconductor Manufacturing Conference (ASMC), April 2006. **
• Xie, X., D. Boning, F. Meyer, R. Rzehak, and P. Wagner, “Analysis and Modeling of Nanotopography Impact in Blanket and Patterned Silicon Wafer Polishing,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Fremont, CA, Feb. 2006.**
• Xie, X., D. Boning, K. Devriendt, and A. S. Lawing, “Modeling of Friction Evolution During STI CMP as Endpoint Signals,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Fremont, CA, Feb. 2006. **
• Boning, D. “Variation and Design for Manufacturability in Advanced Fabrication Processes,” keynote address, International Technology Semiconductor Conference – ISTC 2006, Electrochemical Society, Shanghai, China, March 21-23, 2006. **
• Taylor, H., A. Farahanchi, and D. Boning, “Tool- and pattern-dependent spatial variations in silicon deep reactive ion etch,” International MEMS Conference ’06 (iMEMS), Singapore, May 9-12, 2006. **
• Xie, X., D. Boning, F. Meyer, R. Rzehak, and P. Wagner, “Analysis and Modeling of Nanotopography Impact in Blanket and Patterned Wafer Polishing,” 5th Silicon Wafer SEMI Standards Workshop, SEMICON Europa 2006, Munich, Germany, April 5, 2006. **

2005

• Xie, X. and D. Boning, “Relating Friction in CMP to Topography Evolution,” World Tribology Congress III, paper WTC2005-64115, 2 pgs, Washington, D.C., Sept. 2005. **
• Boning, D. S. and X. Xie, “CMP at the Wafer Edge – Modeling the Interaction Between Wafer Edge Geometry and Polish Performance,” Symposium W: Chemical-Mechanical Planarization – Integration, Technology, and Reliability,” Materials Research Society Spring Meeting, Chemical-Mechanical Planarization – Integration, Technology, and Reliability, MRS Symposium Proceedings vol. 867, pp. 223-234, San Francisco, CA, March 2005. **
• Sun, H., T. Hill, H. Taylor, M. Schmidt, and D. Boning, “A Two-Level Prediction Model for Deep Reactive Ion Etch (DRIE),” International Conference on Micro Electro Mechanical Systems 2005 (MEMS’05), Miami Beach, FL, Jan. 2005. **
• Boning, D., “Modeling of Pattern Dependencies in CMP,” Tutorial, Symposium W: Chemical-Mechanical Planarization – Integration, Technology, and Reliability,” Materials Research Society Spring Meeting, San Francisco, CA, March 2005. **
• Boning, D., L. Pileggi, A. Strojwas, and R. Rutenbar, “Understanding Variation and Its Impact in Devices, Interconnect, and Circuits,” Interconnect Focus Center Workshop, Cambridge, MA, Dec. 2005. **

2004

• Nassif, S. R., D. Boning, and N. Hakim, “The Care and Feeding of your Statistical Static Timer,” International Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 2004. **
• Xie., X. and D. Boning, “A Comparison of Die-Scale CMP Models,” Recent Advances in Chemical Mechanical Planarization I, Annual Meeting of the American Institute of Chemical Engineers, Austin, TX, Nov. 2004. **
• Misra, S., Y. Zhuang, Y. Sampurno, E. Hwang, M. Nasrullah, H. Vaidya, M. Deopura, X. Xie, D. Boning, A. Philipossian and P.K. Roy, “Tribological, Thermal, and Kinetic Characterization and Planarity Performance of Novel Pads for ILD CMP Applications,” VLSI Multilevel Interconnect Conference (VMIC), Waikola, HA, Oct. 2004. **
• Hill, T. F., H. Sun, H. K. Taylor, M. A. Schmidt, and D. S. Boning, “Pattern Density Based Predication for Deep Reactive Ion Etch (DRIE),” Solid-State Sensor, Actuator and Microsystems Workshop, Hilton Head, SC, June 2004. **
• Cai, H., T. Park, D. Boning, Y. Kang, J. Lee, S. K. Kim, and H. Kim, “Coherent Chip-Scale Modeling for Copper CMP Pattern Dependence,” Paper K2.4, Chemical-Mechanical Polishing Symposium, MRS Spring Meeting, San Francisco, April 2004. **
• Xie, X., T. Park, D. Boning, A. Smith, P. Allard, and N. Patel, “Characterizing STI CMP Processes with an STI Test Mask Having Realistic Geometric Shapes,” Paper K9.4, Chemical-Mechanical Polishing Symposium, MRS Spring Meeting, San Francisco, April 2004. **
• Tang, B. and D. Boning, “CMP Modeling and Characterization for Polysilicon MEMS Structures,” Paper K7.6, Chemical-Mechanical Polishing Symposium, MRS Spring Meeting, San Francisco, April 2004. **
• Boning, D., X. Xie, J. Sorooshian, A. Philipossian, D. Stein, and D. Hetherington, “Relationship Between Patterned Wafer Topography Evolution and STI CMP Motor Current Endpoint Signals,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMPMIC), pp. 341-350, Marina Beach, CA, Feb. 2004. **
• Sorooshian, J., A. Philipossian, L. Borucki, R. Timon, D. Stein, D. Hetherington, and D. Boning, “Impact of Pattern Density on the Effective Pressure During STI CMP,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 358-361, Marina Beach, CA, Feb. 2004. **
• Sampurno, Y., Y. Zhuang, Z. Li, A. Philipossian, L. Borucki, and D. Boning, “Novel Method for Direct Measurement of Substrate Temperature During Copper CMP,” 9th Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug., 2004. **

2003

• Sun, H., T. Hill, M. Schmidt, and D. Boning, “Characterization and Modeling of Wafer and Die Level Uniformity in Deep Reactive Ion Etching (DRIE),” paper A10.2, MRS Fall Meeting, Symposium A: Micro- and Nano-systems, Proceedings Vol. 782, Boston, MA, Dec. 2003. **
• Atmaca, E., N. Drego, D. Boning, C. G. Fonstad, L. W. Kahi, and Y. Soon Fatt, “RM^3 Integration of Indium Phosphide Based 1.55 um p-i-n Photodetectors with Silicon CMOS Optical Clock Receiver Circuits,” International Symposium on Compound Semiconductors, pp. 197-198, 2003. **
• Park, T., T. Tugbawa, H. Cai, X. Xie, D. Boning, C. Chidambaram, C. Borst, and G. Shinn, “Integrated Chip-Scale Prediction of Copper Interconnect Topography,” MRS Spring Meeting, Symposium F: Chemical Mechanical Planarization, San Francisco, CA, April 2003. **
• Xie, X., T. Park, Brian Lee, T. Tugbawa, H. Cai and D. Boning, “Re-examining the Physical Basis of Planarization Length in Pattern Density CMP Models,” MRS Spring Meeting, Symposium F: Chemical Mechanical Planarization, San Francisco, CA, April 2003. **
• Sorooshian, J., D. DeNardis, L. Charns, Z. Li, A. Philipossian, and D. Boning, “De-coupling the Chemical and Mechanical Attributes of CMP Through Controlled Removal Rate Versus Temperature Experiments,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Marina Beach, CA, Feb. 2003.
• Xie, X., and D. Boning, “Integrated Modeling of Nanotopography Impact in Patterned STI CMP,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Marina Beach, CA, Feb. 2003. **
• Boning, D., “Test Structures for Timing Variability,” ISQED Tutorial, San Jose CA, March 2003.
• Boning, D., “Pattern Dependent Characterization of Copper Interconnect,” Tutorial, International Conference on Microelectronic Test Structures (ICMTS), Monterey CA, March 2003.
• Boning, D., “Layout Practice Impact on Timing and Yield,” Tutorial, International Symposium on Quality Electronic Design (ISQED), San Jose CA, March 2003.
• Boning, D., “Pattern Dependencies in Copper Electroplating and CMP,” The Planarization and CMP Technical Meeting 2003, Japan Society of Precision Engineering, San Francisco, CA, July 16, 2003.

2002

• Boning, D., J. Panganiban, K. Gonzalez-Valentin, S. Nassif, C. McDowell, A. Gattiker, and F. Liu, “Test Structures for Delay Variability,” ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (Tau 2002), p. 109, Monterey CA, Dec. 2002. **
• Tugbawa, T., T. Park, and D. Boning, “Integrated Chip-Scale Simulation of Pattern Dependencies in Copper Electroplating and Copper Chemical Mechanical Polishing Processes,” International Interconnect Technology Conference (IITC), San Francisco, CA, June 2002. **
• Goodlin, B., H. Sawin, D. Boning, and B. Wise, “Simultaneous Fault Detection and Identification for Plasma Etching Processes,” 201^st Meeting of the Electrochemical Society, International Symposium on Plasma Processing XIV, Abs. 413, Philadelphia, PA, May 2002. **
• Goodlin, B., H. Sawin, and D. Boning, “Quantitative Analysis and Comparison of Endpoint Detection Based on Multiple Wavelength Analysis,” 201^st Meeting of the Electrochemical Society, International Symposium on Plasma Processing XIV, Abs. 415, Philadelphia, PA, May 2002. **
• Lee, B., D. Boning, W. Baylies, N. Poduje, and J. Valley, “Modeling and Mapping of Nanotopography Interactions with CMP,” MRS Spring Meeting, Symposium I: Chemical Mechanical Planarization, paper I1.5, San Francisco, CA, April 2002. ** paper-pdf | talk-ppt | talk-pdf
• Boning, D., B. Lee, N. Poduje, J. Valley, and W. Baylies, “Impact of Nanotopography on STI CMP in Future Technologies,” Workshop on Metrology for Silicon Wafers for 100 nm Technology Generations and Beyond, SEMI/Europa, Munich, April 2002. ** talk-ppt | talk-pdf
• Boning, D. and B. Lee, “Nanotopography Issues in Shallow Trench Isolation CMP,” MRS Bulletin, October 2002. **
• Drego, N., D. Boning, and M. Perrott, “Variation Aware Design of On-Chip Optical Clock Receiver Circuits,” Optical and Electrical High-Speed Digital Clocking Workshop, Stanford University, December 2002. **

2001

• Tugbawa, T., T. Park, B. Lee, D. Boning, P. Lefevre, and J. Nguyen, “Modeling of Pattern Depen­dencies in Abrasive-Free Copper Chemical Mechanical Polishing Processes,” VLSI Multilevel In­terconnection Conference (VMIC), Santa Clara, CA, Nov. 2001. ** pdf | talk-pdf
• Park, T., T. Tugbawa, D. Boning, C. Borst, G. Shinn, and P. R. Chidambaram, “Instantaneous Re­moval Rate in Copper CMP,” Chemical Mechanical Polishing 2001, American Vacuum Society, San Jose, CA, Oct. 11, 2001. **
• Goodlin, B. E., D. S. Boning, and H. H. Sawin, “Multivariate Endpoint Detection – Analysis of Sig­nal to Noise Improvement,” Advanced Equipment Control/Advanced Process Control XIII Sympo­sium (AEC/APC), Banff, Canada, Sept. 2001. **
• Park, T., T. E. Tugbawa, and D. Boning, “Pattern Dependent Modeling of Electroplated Copper Profiles,” International Interconnect Technology Conference (IITC), Burlingame, CA, June 2001. ** paper-pdf | talk-pdf
• Mehrotra, V., and D. Boning, “Technology Scaling Impact of Variation on Clock Skew and Inter­connect Delay,” International Interconnect Technology Conference (IITC), Burlingame, CA, June 2001. **
• Chen, K. H., D. S. Boning, and R. E. Welsch, “Multivariate Statistical Process Control and Signa­ture Analysis Using Eigenfactor Detection Methods,” The 33rd Symposium on the Interface of Computer Science and Statistics, Costa Mesa, CA, June 2001. **
• Sam, S. L., A. Chandrakasan, and D. Boning, “Variation Issues in On-Chip Optical Clock Distri­bution,” Sixth International Workshop on Statistical Methodologies for IC Processes, Devices, and Circuits (IWSM), Kyoto, Japan, June 2001. ** paper-pdf | talk-ppt | talk-pdf
• Lefevre, P., A. Gonzales, T. Brown, T. Tugbawa, T. Park, D. Boning, M. Gostein, and J. Nguyen, “Direct Measurement of Planarization Length For Copper Chemical-mechanical Polishing (CMP) Processes Using A Large Pattern Test Mask,” Symposium M “Chemical-Mechanical Polishing Ad­vances and Future Challenges,” Materials Research Society Spring Meeting, San Francisco, CA, April 16-20, 2001. paper-pdf | talk-ppt | talk-pdf
• Tugbawa, T. E., T. H. Park, D. S. Boning, P. Lefevre, and L. Camilletti, “Modeling of Pattern De­pendencies In Multi-level Copper Chemical-Mechanical Polishing Processes,” Symposium M “Chemical-Mechanical Polishing Advances and Future Challenges,” Materials Research Society Spring Meeting, San Francisco, CA, April 16-20, 2001. ** pdf | talk-pdf
• Lee, B., D. Boning, W. Baylies, N. Poduje, P. Hester, Y. Xia, J. Valley, D. Hetherington, H.-J. Sun, and M. Lacy, “Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods,” Symposium M “Chemical-Mechanical Polishing Advances and Future Challenges,” Materials Research Society Spring Meeting, San Francisco, CA, April 16-20, 2001. ** paper-pdf | talk-pdf
• Lee, B., D. Boning, and L. Economikos, “A Fixed Abrasive CMP Model,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Santa Clara, CA, March 2001. ** paper-pdf | talk-pdf
• Tugbawa, T., T. Park, D. Boning, L. Camilletti, M. Brongo, and P. Lefevre, “Modeling of Pattern Dependencies in Multi-Step Copper Chemical Mechanical Polishing Processes,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Santa Clara, CA, March 2001. **
• Boning, D., T. Tugbawa, and T. Park, “Characterization and Modeling of Pattern Dependencies in Copper CMP,” Semiconductor Fabtech, Edition 13, 2001. **
• Boning, D., B. Lee, T. Tugbawa, and T. Park, “Modeling the Effect of Non-Prestonian Pressure on Pattern Dependencies in CMP,” 6th International Symposium on CMP, Lake Placid, NY, August 2001. **
• Boning, D., B. Lee, T. Tugbawa, and T. Park, “Models for Pattern Dependencies: Capturing Effects in Oxide, STI, and Copper CMP,” Semicon/West Technical Symposium: CMP Technology for ULSI Manufacturing, San Francisco, CA, July 2001. **
• Boning, D., “Modeling of Pattern Dependencies in Multistep Copper CMP Processes,” Characterization Solution for CMP Process Development 2001, Chiba, Japan, December 2001. **

2000

• Goodlin, B. E., D. S. Boning, H. H. Sawin, and M. Yang, “Low Open Area Endpoint Detection of Plasma Etching Processes – Limitations and Signal to Noise Characterization,” Sensors and Control in Plasma Processing, American Vacuum Society, Boston, MA, Oct. 2000.**
• Gower, A., D. Boning, P. Rosenthal, and A. Waldhauer, “Advanced Multi-Objective Control for Epitaxial Silicon Deposition,” Advanced Semiconductor Manufacturing Conference (ASMC), pp. 347-356, Boston, MA, Sept. 2000. **
• Lee, B, T. Gan, D. Boning, P. Hester, N. Poduje, and W. Baylies, “Nanotopography Effects on Chemical Mechanical Polishing for Shallow Trench Isolation,” Advanced Semiconductor Manu­facturing Conference (ASMC), pp. 425-432, Boston, MA, Sept. 2000. **
• Goodlin, B. E., D. S. Boning, and H. H. Sawin, “Signal to Noise Characterization for Endpoint De­tection,” Advanced Equipment Control/Advanced Process Control XII Symposium (AEC/APC), Lake Tahoe, NV, Sept. 2000. **
• Mehrotra, V., S. L. Sam, D. Boning, A. Chandrakasan, R. Valishayee, and S. Nassif, “A Method­ology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Cir­cuit Performance,” Design Automation Conference (DAC), June 2000. **
• Goodlin, B. E., H. H. Sawin, D. S. Boning, and M. Yang, “Edge Effects and Interferometry in Low Open Area Endpoint Detection of Plasma Etching Processes,” Plasma Processing XIII, Electro­chemical Society Meeting, Toronto, May 2000. **
• Lee, B., T. Gan, D. S. Boning, J. David, B. A. Bonner, P. McKeever, and T. H. Osterheld, “Using Wafer-Scale Patterns for CMP Analysis,” Materials Research Society Spring Meeting, Paper E8.8/ D11.8, MRS Spring Meeting, San Francisco, CA, April 2000. **
• White, D., D. Boning, and A. Gower, “Characterization of Endpoint and Wafer-Level Nonuniformity using In-Situ Thermography,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 229-236, Santa Clara, CA, March 2000. **
• Lee, B, D. Hetherington, and D. Boning, “Using Smart Dummy Fill and Selective Reverse Etch­back for Pattern Density EqualizationUsing Smart Dummy Fill and Selective Reverse Etch­back for Pattern Density Equalization,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), Santa Clara, CA, March 2000. **
• Park, T. H, T. Tugbawa, and D. Boning, “Overview of Methods for Characterization of Pattern De­pendencies in Copper CMP,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 197-205, Santa Clara, CA, March 2000. **
• Smith, T., S. J. Fang, G. B. Shinn, J. Stefani, Z. Tang, S. Chang, S. Garza, J. Campbell, and D. Bon­ing, “Improving Within-Die Nonuniformity in Dielectric CMP,” Chemical-Mechanical Planariza­tion for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 362-364, Santa Clara, CA, March 2000. **
• Boning, D. S., “Modeling and Simulation Advances in CMP Processes,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Short Course, Santa Clara, CA, March 1, 2000.
• T. Tugbawa, T. Park, and D. Boning, “Framework for Modeling of Pattern Dependencies in Multi-Step Cu CMP Processes,” CMP Symposium, SEMICON West 2000, July, 2000. **
• B. Lee, D. Boning, W. Baylies, P. Hester, and N. Poduje, “Nanotopography Effects of Chemical Mechanical Polishing on Shallow Trench Isolation,” 5th Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 2000. **
• Maag, B., D. Boning, and B. Voelker, “Assessing the Environmental Impact of Copper CMP,” Semiconductor International, Oct. 2000. **
• Boning, D., B. Lee, W. Baylies, N. Poduje, P. Hester, J. Valley, C. Koliopoulos and D. Hetherington, “Characterization and Modeling of Nanotopography Effects on CMP,” International CMP Symposium 2000, Tokyo, Japan, Dec. 4, 2000. **

1999

• Park, T., T. Tugbawa, D. Boning, S Hymes, T. Brown, K. Smekalin, and G. Schwartz, “Multi-level Pattern Effects in Copper CMP,” Third International Symposium on Chemical Mechanical Polish­ing in IC Device Manufacturing, 196th Electrochemical Society Meeting, Vol. PV99-37, pp. 94-100, Honolulu, HI, Oct. 1999. **
• Hymes, S., T. Brown, P. LeFevre, B. Mikkola, R. Bajaj, T. Park, T. Tugbawa, D. Boning, and J. Nguyen, “Modeling of Topography during 1st Step CMP of Cu-Plated Damascene Structures,” Third International Symposium on Chemical Mechanical Polishing in IC Device Manufacturing, 196th Electrochemical Society Meeting, Vol. PV99-37, pp. 149-157, Honolulu, HI, Oct. 1999.
• Tugbawa, T., T. Park, D. Boning, T. Pan, P. Li, S. Hymes, T. Brown, and L. Camilletti, “A Math­ematical Model of Pattern Dependencies in Copper CMP Processes,” Third International Sympo­sium on Chemical Mechanical Polishing in IC Device Manufacturing, Vol. PV99-37, pp. 605-615, 196th Electrochemical Society Meeting, Honolulu, HI, Oct. 1999. **
• Smith, T., S. Fang, J. Stefani, G. Shinn, D. Boning and S. Butler, “Device Independent Process Con­trol of Chemical-Mechanical Polishing,” Process Control, Diagnostics, and Modeling in Semicon­ductor Device Manufacturing III, Abstract No. 213, 195th Electrochemical Society Meeting, Seattle, WA, May 1999. **
• Sawin, H., M. Le, B. Goodlin, D. White, A. Gower, and D. Boning, “Control of Plasma Processes Based on Full Wafer Interferometry and Multivariate Spectral Analysis of Optical Emission Spec­troscopy,” Process Control, Diagnostics, and Modeling in Semiconductor Device Manufacturing III, Abstract No. 232, 195th Electrochemical Society Meeting, Seattle, WA, May 1999. **
• Smith, T. H., and D. S. Boning, “Process Control in the Semiconductor Industry,” Quality Engi­neering in Semiconductor Manufacturing session, Industrial Engineering Research Conference, Phoenix, AZ, May 22-23, 1999. **
• Boning, D.S., B. Lee, C. Oji, D. Ouma, T. Park, T. Smith, and T. Tugbawa, “Pattern Depen­dent Modeling for CMP Optimization and Control,” Materials Research Society Spring Meeting, Abstract P5.5, Chemical-Mechanical Polishing – Fundamentals and Challenges, MRS Vol. 566, pp. 197-210, San Francisco, CA, April 1999. **
• Hymes, S., K. Smekalin, T. Brown, H. Yeung, M. Joffe, M. Banet, T. Park, T. Tugbawa, D. Boning, J. Nguyen, T. West, and W. Sands, “Determination of the Planarization Distance for Copper CMP Process,” Materials Research Society Spring Meeting, Abstract P5.6, MRS Vol. 566, San Fran­cisco, CA, April 1999. **
• Smith, T. H., D. Boning, S. J. Fang, G. B. Shinn, and J. A. Stefani, “A CMP Model Combining Den­sity and Time Dependencies,” Chemical-Mechanical Planarization for ULSI Multilevel Intercon­nect Conference (CMP-MIC), pp. 97-104, Santa Clara, CA, Feb. 1999. **
• Park, T., T. Tugbawa, D. Boning, J. Chung, S. Hymes, R. Muralidhar, B. Wilks, K. Smekalin, G. Bersuker, “Electrical Characterization of Copper Chemical Mechanical Polishing,” Chemical-Me­chanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 184-191, Santa Clara, CA, Feb. 1999. **
• Fang, S. J., G. B. Shinn, T. H. Smith, and D. Boning, “Advanced Process Control in Dielectric Chemical Mechanical Polishing,” Chemical-Mechanical Planarization for ULSI Multilevel Inter­connect Conference (CMP-MIC), pp. 367-374, Santa Clara, CA, Feb. 1999. **
• Pan, J. T., P. Li, K. Wijekoon, S. Tsai, F. Redeker, T. Park, T. Tugbawa, and D. Boning, “Copper CMP and Process Control,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 423-429, Santa Clara, CA, Feb. 1999. **
• Chiarello, R., A. Muscat, D. Boning, K. Gleason, S. Karecki, and S. Raghavan, “Multidisciplinary Approaches Target ESH&H,” Solid State Technology, pp. 62-66, Feb. 1999.
• Boning, D., “A Methodology for Modeling and Characterization of Dielectric CMP Processes,” The CMP Technical Symposium 1999, pp. 23-38, Tokyo, Japan, June 1999.
• Smith, T., S. Fang, J. Stefani, G. Shinn, S. W. Butler, and D. S. Boning, “Device Independent Run by Run CMP Process Control,” The CMP Technical Symposium 1999, pp. 39-50, Tokyo, Japan, June 1999. **
• Park, T., T. Tugbawa, D. Boning, and S. Hymes, “Characterization of Pattern Dependent Variation in Copper CMP,” The CMP Technical Symposium 1999, pp. 79-90, Tokyo, Japan, June 1999. **
• Boning, D., T. Park, T. Tugbawa, S. Hymes, and T. Pan, “Modeling of Copper Chemical Mechanical Polishing,” 4th Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 1999.
• Poduje, N., W. Baylies, B. Lee, T. Gan, and D. Boning, “Nanotopology Effects in Chemical Mechanical Polishing,” SEMI-AWG Nanotopography Workshop, Tokyo, Japan, Nov. 29, 1999. **

1998

• Mehrotra, V., S. Nassif, D. Boning, and J. Chung, “Modeling the Effects of Manufacturing Varia­tion on High-Speed Microprocessor Interconnect Performance,” International Electron Devic­es Meeting (IEDM), pp. 767-770, San Francisco. CA, Dec. 1998. **
• Smith, T. H., S. J. Fang, J. A. Stefani, G. B. Shinn, D. S. Boning, S. W. Butler, “NOVA On-Line CMP Metrology and Its Use for Lot-to-Lot Process Control,” 45th National Symposium of the American Vacuum Society, Baltimore, MD, Nov. 1998. **
• White, D. A., B. E. Goodlin, A. Gower, D. Boning, H. Sawin, “Multivariate Spectral Analysis of Optical Emission Spectroscopy for use in Low-Open Area Endpoint Detection,” 45th National Symposium of the American Vacuum Society, Baltimore, MD, Nov. 1998. **
• Ouma, D., D. Boning, J. Chung, G. Shinn, L. Olsen, and J. Clark, “An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization,” International Interconnect Technol­ogy Conference (IITC), pp. 67-69, San Francisco, CA, June 1998. **
• Smith, T., C. Oji, D. Boning, and J. Chung, “Bias and Variance in Multiple Response Surface Mod­eling,” Third International Workshop on Statistical Metrology (IWSM), pp. 60-63, Honolulu, HI, June 1998. **
• Park, T., T. Tugbawa, J. Yoon, D. Boning, J. Chung, R. Muralidhar, S. Hymes, Y. Gotkis, S. Alam­gir, R. Walesa, L. Shumway, G. Wu, F. Zhang, R. Kistler, and J. Hawkins, “Pattern and Process Dependencies in Copper Damascene Chemical Mechanical Polishing Processes,” VLSI Multilevel Interconnect Conference (VMIC), pp. 437-442, Santa Clara, CA, June 1998. **
• Pan, J. T., D. Ouma, P. Li, D. Boning, F. Redecker, J. Chung, and J. Whitby, “Planarization and Integration of Shallow Trench IsolationPlanarization and Integration of Shallow Trench Isolation,” VLSI Multilevel Interconnect Conference (VMIC), pp. 467-472, Santa Clara, CA, June 1998. **
• Boning, D., D. Ouma, and J. Chung, “Extraction of Planarization Length and Response Function in Chemical-Mechanical Polishing,” Materials Research Society 1998 Spring Meeting, Abstract Q5.1, pp. 286-287, San Francisco, CA, May 1998. **
• Boning, D., and J. Chung, “Statistical Metrology – Measurement and Modeling of Variation for Advanced Process Development and Design Rule Generation,” 1998 International Conference on Characterization and Metrology for ULSI Technology, pp. 395-404, Gaithersburg, MD, March 1998. **
• Ouma, D., C. Oji, D. Boning, J. Chung, D. Hetherington, and P. Merkle, “Effect of High Relative Speed on Planarization Length in Oxide Chemical Mechanical Polishing,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 20-27, Santa Clara, CA, Feb. 1998. ** 
• Park, T., D. Boning, and J. Chung, “Characterization and Modeling of Oxide CMP,” International CMP Technical Symposium for ULSI Multilevel Interconnection, Seoul, Korea, January, 1998. **
• Boning, D. S., “CMP Pattern Dependent Modeling Developments,” VLSI Multilevel Interconnection State of the Art Seminar, Santa Clara, CA, June 1998.
• Rosenthal, P. R., P. A. Rosenthal, V. Yakovlev, G. Barna, B. Van Eck, C.M. Nelson, M. L. Spartz, A. Gower, T. Smith, D. Boning, A. Waldhauer, W. Aarts, K. Paul Muller, J. Moyne, J. Mott, R. Mundt, A Perry, A. Weber, R. Bunkofske, “The Next Steps in Advanced Process Control,” Future Fab International, July 1998.
• Boning, D., “Metrics and Modeling for Pattern-Dependent Planarization Performance,” CMP Technology for ULSI Interconnection, Semicon/West Technical Sessions, San Francisco, CA, July 1998.
• Chen, H. and D. Boning, “Data-Rich Multivariate Detection/Diagnosis Using Extensions to Principal Components Analysis,” AISE Workshop on Advanced Technologies in Modeling, Scheduling, and Control, Cambridge, MA, July 1998. **
• Nishimoto, A., T. Smith, D. Ouma, E. Stuckey, and D. Boning, “An in-situ sensor for reduced consumable usage through control of CMP,” Extended Abstracts, TechCon’98, Semiconductor Research Corporation, Las Vegas, NV, Sept. 1998. **
• Boning, D., D. Ouma, T. Park, T. Tugbawa, B. Lee, C. Oji, J. Yoon, and T. Smith, “Recent Progress in Pattern Dependent CMP Modeling,” 3rd Annual Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 16-19, 1998.
• Ouma, D. O., T. Park, and D. Boning, “MIT CMP Characterization Masks and Applications,” CMP 98 Symposium, Tokyo, Japan, Dec. 1998. **
• Sachs, E. M., N. M. Patrikalakis, D. Boning, M. J. Cima, T. R. Jackson, and R. Resnick, “The Distributed Design and Fabrication of Metal Parts and Tooling by 3D Printing,” Proceedings of the 1998 NSF Design and Manufacturing Grantees Conference, pp. 35-36, Monterrey, Mexico, Jan. 1998.

1997

• Stine, B. E., V. Mehrotra, D. S. Boning, J. E. Chung, and D. J. Ciplickas, “A Simulation Method­ology for Assessing the Impact of Spatial/Pattern Dependent Variation on Circuit Performance,” In­ternational Electron Devices Meeting (IEDM), pp. 133-136, Wash. DC, Dec. 1997. **
• Chung, J. E. and D. S. Boning, “CMP ILD Thickness Variation Characterization and Data Analy­sis,” Third International CMP Technical Symposium, Tokyo, Japan, Dec. 1997. **
• Smith, T. and D. Boning, “Non-Periodic Lot Processing, Random Measurement Delays, and Inter­mittent Lot Processing with an Extended Predictor Corrector Controller,” 44th National Sympo­sium of the American Vacuum Society, San Jose, CA, Oct. 1997. **
• Le, M., T. Smith, D. Boning, and H. Sawin, “Run-to-Run Process Control and Endpoint Detection on a Dual-Coil TCP with FWI and OES,” 44th National Symposium of the American Vacuum So­ciety, San Jose, CA, Oct. 1997. **
• Nakagawa, O.S., S.-Y. Oh, F. Eschbach, G. Ray, P. Nikkel, R. Divecha, B. Stine, D. Ouma, D. Bon­ing, and J. Chung, “Modeling of CMP-induced Pattern-dependent ILD Thickness Variation in Mul­tilevel Metallization System,” Advanced Metallization Conference (AMC), San Diego, CA, Oct. 1997. **
• Maury, A., D. Ouma, D. Boning, and J. Chung, “A Modification to Preston’s Equation and Impact on Pattern Density Effect Modeling,” Advanced Metallization Conference (AMC), San Diego, CA, Oct. 1997. **
• Ouma, D., B. Stine, R. Divecha, D. Boning, J. Chung, G. Shinn, I. Ali, and J. Clark, “Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing,” Manufacturing Yield, Reli­ability, and Failure Analysis session, SPIE 1997 Symposium on Microelectronic Manufacturing, Austin TX, Oct. 1997. **
• Muthukrishnan, N. M., S. Prasad, B. E. Stine, W. Loh, R. Nagahara, J. E. Chung, D. S. Boning, “Evaluation of pad life in chemical mechanical polishing process using statistical metrology,” Man­ufacturing Yield, Reliability, and Failure Analysis session, SPIE 1997 Symposium on Microelec­tronic Manufacturing, Austin TX, Oct. 1997.
• Boning, D., “Fundamentals and Applications of Run by Run Process Control,” Tutorial II, Ad­vanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SEMATECH, Incline Vil­lage, NV, Sept. 1997.
• Stefani, J., S. Butler, T. Smith, and D. Boning, “Advanced Process Control of Sputter Depositions”, Advanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SEMATECH, Incline Vil­lage, NV, Sept. 1997. **
• Rosenthal, P., P. Solomon, S. Charpenay, A. Bonanno, W. Zhang, W. Eikleberry, A. Gower, T. Smith, D. Boning, and A. Waldhauer, “Run to Run Control of A Single Wafer Epitaxial Silicon Fabrication Process,” Advanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SE­MATECH, Incline Village, NV, Sept. 1997. **
• Stine, B., D. Boning, J. Chung, D. Ciplickas, and J. Kibarian, “Simulating the Impact of Poly-CD Wafer-Level and Die-Level Variation On Circuit Performance,” Second International Workshop on Statistical Metrology (IWSM), pp. 24 -27, Kyoto, Japan, June 1997. **
• Stefani, J., S. W. Butler, T. Smith, and D. Boning, “Exponentially Weighted Moving Average-Based Control of Metal Sputter Deposition Processes for Semiconductor Manufacturing,” 4th In­ternational Applied Statistics in Industry Conference, Kansas City, MO, June 1997. **
• Smith, T., A. Gower, and D. Boning, “A Matrix Math Library for Java,” ACM 1997 Workshop on Java for Science and Engineering Computation, Las Vegas, June 1997. **
• Le, M., T. Smith, D. Boning, and H. Sawin, “Run-to-Run Process Control on a Dual-Coil Trans­former Coupled Plasma Etcher with Full Wafer Interferometry and Spatially Resolved Optical Emission Spectrometer,” Proc. of the Second International Symposium on Process Control, Diag­nostics, and Modeling in Semiconductor Manufacturing, Electrochemical Society Proc. Vol. 97-9, pp. 3-10, Montreal, May 1997. **
• Smith, T., D. Boning, J. Stefani, and S. W. Butler, “Run by Run Advanced Process Control of Metal Sputter Deposition,” Proc. of the Second International Symposium on Process Control, Diagnos­tics, and Modeling in Semiconductor Manufacturing, Electrochemical Society Proc. Vol. 97-9, pp. 11-18, Montreal, May 1997. **
• Boning, D., J. Chung, D. Ouma, and R. Divecha, “Spatial Variation in Semiconductor Processes: Modeling for Control,” Proc. of the Second International Symposium on Process Control, Diagnos­tics, and Modeling in Semiconductor Manufacturing, Electrochemical Society Proc. Vol. 97-9, pp.72-83, Montreal, May 1997. **
• Stine, B., D. Ouma, R. Divecha, D. Boning, J. Chung, D. L. Hetherington, I. Ali, G. Shinn, J. Clark, O.S. Nakagawa, and S.-Y. Oh, “A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Confer­ence (CMP-MIC), pp. 266-273, Santa Clara, CA, Feb. 1997. **
• Divecha, R., B. Stine, D. Ouma, J. Yoon, D. Boning, J. Chung, O.S. Nakagawa, and S.-Y. Oh, “Effect Of Fine-Line Density And Pitch On Interconnect Ild Thickness Variation In Oxide Cmp Processes,” Chemical-Mechanical Planarization for ULSI Multilevel Interconnect Conference (CMP-MIC), pp. 29-36, Santa Clara, CA, Feb. 1997. ** 
• Boning, D. and J. Chung, “Statistical Metrology: Tools for Understanding Variation,” Future Fab International, vol. 1, no. 2, pp. 323-328, Jan. 1997. **
• Stine, B. E., D. S. Boning, J. E. Chung, and D. Hetherington, “Rapid Characterization and Modeling of Spatial Variation: A CMP Case Study,” Proceedings KLA/Tencor Yield Management Seminar, Semicon/West, San Francisco, CA, July 1997. ** 
• Boning, D., “Fundamentals and Applications of Run by Run Process Control,” Tutorial II, Advanced Equipment Control/Advanced Process Control Workshop IX (AEC/APC), SEMATECH, Incline Village, NV, Sept. 1997.

1996

• McIlrath, M.B., D. Boning, and D. Troxel, “Architecture for Distributed Design and Fabrication,” Plug and Play Software for Agile Manufacturing, Proc. SPIE International Symposium on Intelli­gent Systems and Advanced Manufacturing, vol. 2913, pp. 134-147, Boston, MA, Nov. 1996. **
• Gower, A., D. Boning, and M. McIlrath, “A Flexible Distributed Architecture for Semiconductor Process Control and Experimentation,” Open Architecture Control Systems and Standards, SPIE International Symposium on Intelligent Systems and Advanced Manufacturing, pp. 146-158, Bos­ton, MA, Nov. 1996. ** 
• Ning, Z., J. R. Moyne, T. Smith, D. Boning, E. Del Castillo, J.-Y. Yeh, and A. Hurwitz, “A Com­parative Analysis of Run-to-Run Control Algorithms in the Semiconductor Manufacturing Indus­try,” SEMI/IEEE Advanced Semiconductor Manufacturing Conference & Workshop (ASMC), pp. 375 -381, Cambridge, MA, Nov. 1996. **
• Smith, T., and D. Boning, “A Self-Tuning EWMA Controller Utilizing Artificial Neural Network Function Approximation Techniques,” IEEE International Electronics Manufacturing Technology Sympo­sium (IEMT), pp. 355-363, Austin, TX, Oct. 1996. ** 
• Boning, D., and J. Chung, “Statistical Metrology – Tools for Understanding Spatial Variation,” Manufacturing Yield, Reliability, and Failure Analysis session, SPIE 1996 Symposium on Micro­electronic Manufacturing, Austin TX, Oct. 1996. **
• Stine, B., D. Boning, J. Chung, D. Bell, and E. Equi, “Inter- and Intra-die Polysilicon Critical Di­mension Variation,” Manufacturing Yield, Reliability, and Failure Analysis session, SPIE 1996 Symposium on Microelectronic Manufacturing, Austin TX, Oct. 1996. **
• Ouma, D., B. Stine, R. Divecha, D. Boning, J. Chung, I. Ali, and M. Islamraja, “Using Variation Decomposition Analysis to Determine the Effect of Process on Wafer and Die-Level Uniformities in CMP,” First International Symposium on Chemical Mechanical Planarization (CMP) in IC De­vice Manufacturing, 190th Electrochemical Society Meeting, San Antonio, TX, Oct. 6-11, 1996. **
• Wong, K.S., D. Boning. H. Sawin, S. Butler, and E. Sachs, “Endpoint prediction for polysilicon plasma etching via optical emission interferometry,” Manufacturing Science and Technology Ses­sion, 43rd National Symposium of the American Vacuum Society, Philadelphia, PA, Oct. 1996. **
• Smith, T and D. Boning, “An Artificial Neural Network EWMA Controller for Semiconductor Pro­cesses,” Manufacturing Science and Technology Session, 43rd National Symposium of the Amer­ican Vacuum Society, Philadelphia, PA, Oct. 1996. **
• Boning, D., T. Smith, A. Gower, M. Le, H. Sawin, J. Moyne, and A. Hurwitz, “Run by Run Control: Algorithmic and Application Advances,” Advanced Equipment Control/Advanced Process Control Workshop VIII (AEC/APC), SEMATECH, Sante Fe, NM, Oct. 1996. **
• Losleben, P., and D. Boning, “A New Semiconductor Research Paradigm using Internet Collabo­ration,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Tokyo, Japan, Sept. 1996. **
• Divecha, R. R., B. E. Stine, E. C. Chang, D. O. Ouma, D. S. Boning, J. E. Chung, O. S. Nakagawa, S.-Y. Oh, S. Prasad, W. Loh, and A. Kapoor, “Assessing and Characterizing Inter- and Intra-die Variation Using a Statistical Metrology Framework- A CMP Case Study” First International Work­shop on Statistical Metrology (IWSM), pp. 9-12, Honolulu, HI, June 1996. ** (figures)
• Smith, T., D. Boning, J. Moyne, A. Hurwitz, and J. Curry, “Compensating for CMP Pad Wear Using Run by Run Feedback Control,” VLSI Multilevel Interconnect Conference (VMIC), pp. 437-440, Santa Clara, CA, June 1996. ** 
• Stine, B., D. Boning, J. Chung, L. Camilletti, E. Equi, S. Prasad, W. Loh, and A. Kapoor, “The Role of Dummy Fill Patterning Practices on Intra-Die ILD Thickness Variation in CMP Processes,” VLSI Multilevel Interconnect Conference (VMIC), pp. 421-423, Santa Clara, CA, June 1996. **
• Divecha, R. R., B. E. Stine, D. O. Ouma, D. Boning, J. Chung, O. S. Nakagawa, S.-Y. Oh, and D. L. Hetherington, “Comparison of Oxide Planarization Pattern Dependencies between Two Different CMP Tools Using Statistical Metrology,” VLSI Multilevel Interconnect Conference (VMIC), pp. 427-430, Santa Clara, CA, June 1996. **
• Prasad, S., W. Loh, A. Kapoor, E. Chang, B. Stine, D. Boning, and J. Chung, “Statistical Metrology for Characterizing CMP Processes,” European Materials Research Society Spring Meeting, Stras­bourg, France, June 4-7, 1996. **
• Wong, K. S., D. S. Boning, and H. H. Sawin, “On Endpoint Detection of Plasma Etching via Optical Emission Interferometry,” 189th Electrochemical Society Meeting, p. 302, Los Angeles, CA, May 1996. **
• Moyne, J.R., J. Curry, M. Lacy, D. Boning, T. Smith, and A. Hurwitz, “Application of an Automated CMP Run-to-Run Architecture to Nonlinear CMP Process Control,” Clarkson Workshop on Chemical Mechanical Polishing, Lake Placid, NY, Aug. 1996. **

1995

• Chang, E, B. Stine, T. Maung, R. Divecha, D. Boning, J. Chung, K. Chang, G. Ray, D. Bradbury, S. Oh, and D. Bartelink, “Using a Statistical Metrology Framework to Identify Systematic and Random Sources of Die- and Wafer-level ILD Thickness Variation in CMP Processes,” International Electron Devices Meeting (IEDM), pp. 499-502, Wash. D.C., Dec. 1995. ** (figures)
• Boning, D., W. Moyne, T. Smith, J. Moyne, and A. Hurwitz, “Practical Issues in Run by Run Pro­cess Control,” 1995 SEMI/IEEE Advanced Semiconductor Manufacturing Conference and Work­shop (ASMC), pp. 201-208, Cambridge, MA, Nov. 1995. **
• Boning, D., A. Hurwitz, J. Moyne, W. Moyne, S. Shellman, T. Smith, J. Taylor, and R. Telfeyan, “Run by Run Control of Chemical Mechanical Polishing,” Proc. of IEEE International Electronics Manu­facturing Technology Symposium (IEMT), pp. 81-87, Austin, TX, Oct. 1995. **
• Boning, D., N. Chaudhry, A. Hurwitz, J. Moyne, W. Moyne, S. Shellman, T. Smith, and R. Telfey­an, “A Multi-level Approach to the Control of a Chemical Mechanical Planarization Process,” 42nd National Symposium of the American Vacuum Society, Abstract #1022, Minneapolis, MN, Oct. 1995. ** 
• Wong, K.S. and D. S. Boning, “On In-Situ Etch Rate Estimation from Interferometric Signals,” Proc. of Process Control, Diagnostics, and Modeling in Semiconductor Manufacturing I, 187th Electrochemical Society Meeting, pp. 360-371, Reno, NV, May 1995. ** 
• Losleben, P. and D. Boning, “A New Research Paradigm using Internet Collaboration, or Building a National Research Enterprise,” Hierarchical Technology CAD – Process, Device, and Circuits, Stanford University, Stanford, CA, Aug. 1995. **
• Chang, E, B. Stine, T. Maung, R. Divecha, D. Boning, J. Chung, K. Chang, G. Ray, D. Bradbury, S. Oh, and D. Bartelink, “Using a Statistical Metrology Framework to Identify Random and Systematic Sources of Intra-Die ILD Thickness Variation for CMP Processes,” SEMATECH Statistical Metrology Workshop, Austin TX, August 22, 1995. **

1994

• Boning, D. S., T. Maung, J. Chung, K.-J. Chang, S.-Y. Oh, and D. Bartelink, “Statistical metrology of interlevel dielectric thickness variation,” Proceedings of the SPIE Symposium on Microelectron­ics Manufacturing, SPIE Vol. 2334, pp. 316-327, Austin, TX, Oct. 1994. **
• Boning, D. S., J. L. Claman, K. S. Wong, T. J. Dalton, and H. H. Sawin, “Plasma Etch Endpoint via Interferometric Imaging,” Advanced Equipment Control/Advanced Process Control Workshop VI (AEC/APC), SEMATECH, San Antonio, TX, Sept. 1994. **
• Boning, D. S. and M. B. McIlrath, “Conceptual Graphs and Manufacturing Processes,” Second In­ternational Conference on Conceptual Structures (ICCS), Proceedings Supplement, pp. 1-15, College Park, MD, Aug., 1994.
• Boning, D. S., J. L. Claman, K. S. Wong, T. J. Dalton, and H. H. Sawin, “Plasma Etch Endpoint via Interferometric Imaging,” Proceedings of the American Control Conference (ACC), pp. 897-911, Balti­more, MD, June 1994. **

1993

• Rodder, M., A. Chatterjee, D. Boning, and I. C. Chen, “Transistor Design with TCAD Tuning and Device Optimization for Process/Device Synthesis,” Proceedings of Technical Papers, 1993 Int. Symp. on VLSI Technology, Systems, and Applications, paper A7, pp 29-33, Taipei, Taiwan, May, 1993.
• Gopalarao, K., U. DasGupta, D. Boning, P. Mozumder, V. Chandramouli, and R. Jain, “An Inte­grated Technology CAD System for Process and Device Designers,” VLSI Design, pp. 287-292, Bombay, India, Jan. 1993.
• Boning, D., S. Ha, and E. Sachs, “On-Line Control of Uniformity in Single-Wafer Plasma Etch Processes,” Extended Abstracts, TechCon’93, pp. 19-21, Semiconductor Research Corporation, Atlanta, GA, Sept. 1993. **

1992

• Boning, D. S., G. Chin, R. Cottle, W. Dietrich, S. Duvall, M. Giles, R. Harris, M. Karasick, N. Kha­lil, M. Law, L. Nackman, S. Nassif, V. T. Rajan, D. Schroeder, R. Tremain, D. Walker, R. Wang, and A. Wong, “Developing and Integrating TCAD Applications with the Semiconductor Wafer Representation,” Workshop on Numerical Modeling of Processes and Devices for Integrated Cir­cuits: NUPAD IV Technical Digest, pp. 199-200, Seattle, WA, May 1992.

1991

• Chin, G., W. Dietrich, Jr., D. Boning, A. Wong, A. Neureuther, and R. Dutton, “Linking TCAD to EDA – Benefits and Issues,” 28th Design Automation Conference (DAC), pp. 573-578, Orlando, FL, June 1991.

1990

• Maseeh, F., R. M. Harris, D. S. Boning, M. L. Heytens, S. A. Gelston, and S. D. Senturia, “Appli­cation of Mechanical Technology CAD to Microelectronic Device Design and Manufacturing,” Proceedings of the Ninth IEEE/CHMT International Electronics Manufacturing Technology Symposium (IEMT), pp. 350-355, Washington DC, Oct. 1990.
• McIlrath, M. B., D. E. Troxel, D. S. Boning, M. L. Heytens, and P. Penfield Jr., “CAFE – The M.I.T. Computer Aided Fabrication Environment,” Proceedings of the Ninth IEEE/CHMT International Electronics Manufacturing Technology Symposium (IEMT), pp. 224-230, Washington D.C., Oct. 1990.
• Wong, A. S., D. S. Boning, M. Heytens, and A. R. Neureuther, “The Intertool Profile Interchange Format,” Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits: NU­PAD III Technical Digest, pp. 61-62, Honolulu, HI, June 3-4, 1990.
• McIlrath, M. B. and D. S. Boning, “Integrating Semiconductor Process Design and Manufacture Using a Unified Process Flow Representation,” Proceedings of the Second International Confer­ence on Computer Integrated Manufacturing, pp. 224-230, IEEE Press, Troy, NY, May 21-23, 1990.

1986

• Boning, D. S., “Wafer Profile Interchange Format,” SRC Workshop on System Architecture for CIM, U.C. Berkeley, November 11-14, 1986.

1985

• Boning, D. S. and D. A. Antoniadis, “MASTIF – A Workstation Approach to Fabrication Process Design,” International Conference on Computer-Aided Design (IICCAD), pp. 280-282, Santa Clara, Nov., 1985.

** Outgrowth of supervised student research