2019

• H. Chen and D. S. Boning, “Machine Learning Approaches for IC Manufacturing Yield Enhancement” in Machine Learning in VLSI Computer-Aided Design, pp 175-199. Springer, March 2019.

2015

• Fan, W. and D. Boning, “Multiscale Modeling of CMP,” in Advances in Chemical Mechanical Planarization (CMP), ed. S. V. Babu, Woodhead Publishing Limited, 2015.

2008

• Orshansky, M., S. Nassif, and D. Boning, Statistical Design and Design for Manufacturability: A Constructive Approach, 316 pp., Springer, February 2008.

2007

• Shinn, G. B., V. Korthuis, G. Grover, S. Fang, and D. S. Boning, “Chemical-Mechanical Polishing,” in Handbook of Semiconductor Manufacturing Technology, Ed. R. Doering and Y. Nishi, 2nd Edition, CRC Press, July 2007.

2005

• Kinoshita, M., H. Izumi, H. Hiyama, T. Doy, A. Philipossian, D. Boning, and F. Shadman, Planarization Technical Term Dictionary, Planarization and CMP Technical Committee, JSPE, Japan, March 2005.

2004

• Boning, D., J. W. Bartha, G. Shinn, I. Vos, and A. Philipossian, Eds., Advances in Chemical-Mechanical Polishing, Materials Research Society, Volume 816, 2004.
• Boning, D. and D. Hetherington, “Patterned Wafer Effects,” in Chemical-Mechanical Planarization of Semiconductor Materials, Ed. M. R. Oliver, Springer-Verlag, 2004.

2003

• Boning, D. S., K. Devriendt, M. R. Oliver, D. J. Stein, and I. Vos, Eds., Chemical-Mechanical Planarization, Materials Research Society, Volume 767, 2003.

2001

• Smith, T. H., D. S. Boning, and J. Moyne, “Process Control in the Semiconductor Industry,” in Run-to-Run Control in Semiconductor Manufacturing, Eds. J. Moyne, E. del Castillo, and A. M. Hurwitz, pp. 15-44, CRC Press, Boca Raton, 2001.
• Ning, Z., J. Moyne, T. Smith, D. Boning, E. del Castillo, J.-Y. Yeh, and A. M. Hurwitz, “PA Comparative Analysis of Run-to-Run Control Algorithms in the Semiconductor Manufacturing Industry,” in Run-to-Run Control in Semiconductor Manufacturing, Eds. J. Moyne, E. del Castillo, and A. M. Hurwitz, pp. 101-111, CRC Press, Boca Raton, 2001.
• Boning, D. “Statistical Metrology, with Applications to Interconnect and Yield Modeling,” in Handbook of Silicon Semiconductor Metrology, Ed. A. Diebold, Marcel Dekker, Inc., 2001.

2000

• Boning, D., and S. Nassif, “Models of Process Variations in Device and Interconnect,” in Design of High Performance Microprocessor Circuits, Eds. A. Chandrakasan, W. Bowhill and F. Fox, IEEE Press, 2000.
• Boning, D. S., and O. Ouma, “Modeling and Simulation,” in Chemical Mechanical Polishing in Silicon Processing, Semiconductors and Semimetals, vol. 63, Eds. S. H. Li and B. Miller, Academic Press, San Diego, CA, 2000.

1999

• Boning, D. S., J. Stefani, and S. W. Butler, “Statistical Methods for Semiconductor Manufacturing,” in Encyclopedia of Electrical and Electronics Engineering, vol. 20, pp. 463-479, J. G. Webster, Ed., John Wiley & Sons, 1999.
• Troxel, D. E, D. S. Boning, and M. B. McIlrath, “Process Flow Representations for Semiconductor Manufacturing,” in Encyclopedia of Electrical and Electronics Engineering, vol. 19, pp. 139-147, J. G. Webster, Ed., John Wiley & Sons, 1999.